Analog switch with a low flatness operating characteristic

ABSTRACT

An analog switch includes a transistor whose source connected to a signal input and whose drain is connected to a signal output. An output of a gate control circuit is connected to the transistor gate. A first input of the gate control circuit is connected to the source of the transistor. The gate control circuit responds to a logic transition of an enable signal received at a second input by pre-charging a substantially constant gate-to-source voltage across the transistor. This voltage is stored by a gate-to-source connected capacitor. In one steady-state logic condition of the enable signal, the gate control circuit operates to turn off the transistor. In another steady-state logic condition of the enable signal, the gate control circuit permits the signal received at the signal input to drive the gate of the transistor with a voltage offset by the substantially constant gate-to-source voltage stored on the capacitor.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The present invention relates generally to analog switches, and moreparticularly to MOS analog switches.

2. Description of Related Art

Reference is now made to FIG. 1 which shows a schematic diagram of aprior art MOS analog switch 10. The switch 10 is formed from an NMOStransistor 12 and a PMOS transistor 14 that are connected in parallel.More specifically, the source of the NMOS transistor 12 is connected tothe drain of the PMOS transistor 14 (at node 16), and the drain of theNMOS transistor 12 is connected to the source of the PMOS transistor 14(at node 18). The input signal at the terminal IN is applied to node 16and the output signal at the terminal OUT is taken from node 18. Acontrol signal at the terminal CONTROL is applied to gate of NMOStransistor 12, while the complement of the control signal is applied tothe gate of the PMOS transistor 14 through the operation of an inverter20. When the control signal is logic low, the NMOS transistor 12 andPMOS transistor 14 are both turned off so as to isolate the inputterminal IN from the output terminal OUT. When the control signal islogic high, however, the NMOS transistor 12 and PMOS transistor 14 areboth turned on, and a signal at the input terminal IN is coupled by theanalog switch 10 to the output terminal OUT.

The analog switch 10 is used in many applications. For example, theswitch 10 is used in audio applications to control passage of an analogaudio signal from IN to OUT. When used in audio applications, however,it is important that the analog switch 10 exhibit a low flatnesscharacteristic. “Flatness” refers to the difference between the maximumvalue of on-resistance for the switch 10 and the minimum value ofon-resistance for the switch 10 over a range of voltage input levels.The lower the flatness (i.e., the more flat the on-resistance of theswitch 10 as a function of input voltage), the better; especially inaudio applications where flatness can be correlated to sound quality(and non-flatness correlated to signal distortion). The circuit of FIG.1 does not exhibit a flatness which is acceptable for many audio (andother) applications.

Reference is now made to FIG. 2 which shows a schematic diagram of aprior art MOS analog switch 50 (as taught by U.S. Pat. No. 6,154,085,the disclosure of which is hereby incorporated by reference). The switch50 has an improved low flatness operating characteristic in comparisonto switch 10 of FIG. 1. This is accomplished by regulating the gatevoltage according to the signal source. First NMOS transistor 52 has itssource coupled to the input terminal IN, and its drain coupled to theoutput terminal OUT. Second NMOS transistor 54 has its source coupled tothe input terminal IN and its drain coupled to node 56. Third NMOStransistor 58 has its source coupled to the node 56 and its draincoupled to the output terminal OUT. A control signal at the terminalCONTROL is applied to the gates of transistors 52, 54 and 58. Node 56 isfurther coupled to the bulk terminals (substrate wells) of transistors52, 54 and 58. The switch 50 further includes a level shifter 60 whoseinput is coupled to the node 56 and whose output is coupled to the gatesof transistors 52, 54 and 58 through an optional resistor 62.

When the switch 50 is turned on by the control signal, the circuitfunctions to provide a constant gate drive to NMOS transistor 52,regardless of the input signal received at terminal IN, in order tomaintain a substantially constant on-resistance for the switch 50 (i.e.,achieve low flatness). The level shifter 60 accomplishes this byproviding a constant gate-to-source voltage relative to the midpoint ofthe source-to-drain voltage of transistor 52. The transistors 54 and 58provide a voltage at node 56 which is at the midpoint between the sourcevoltage and drain voltage of transistor 52. The level shifter 60 shiftsthe signal voltage at the input terminal IN by an amount equal to thedesired gate-to-source voltage of the transistor 52, and provides thefixed gate-to-source voltage with respect to the source-to-drainvoltage.

There are limitations with respect to the switch 50 of FIG. 2. The levelshifter 60 requires a constant current to operate (see, '085 patent,FIG. 3), and this not preferred in battery powered (for example, mobile)applications. Additionally, if the input signal at terminal IN goes tofar negative (for example, −1 Volt), the output of the level shifter 60will be clamped to zero volts.

There is accordingly a need in the art for an improved analog switchexhibiting a low flatness operating characteristic and suitable for usein battery powered applications.

SUMMARY OF THE INVENTION

In an embodiment, a circuit comprises: a first transistor coupledbetween a signal input and an output; a second transistor coupledbetween the signal input and a node; a third transistor coupled betweenthe node and the output; and a gate control circuit having an outputcoupled to the gates of the first, second and third transistors, andhaving a first input coupled to the signal input, the gate controlcircuit comprising a capacitor coupled across the gate-to-source of thefirst transistor between the first input and the output of the gatecontrol circuit, wherein a voltage stored across the capacitor sets asubstantially constant gate-to-source voltage of the first transistorregardless of a signal at the signal input.

In another embodiment, a circuit comprises: a first transistor having asource coupled to a signal input, a drain coupled to a signal output,and a gate; and a gate control circuit having an output coupled to thegate of the first transistor, and having a first input coupled to thesource of the first transistor, the gate control circuit adapted toprovide a substantially constant voltage difference between the gate andsource of the first transistor and further lacking a static dischargepath.

In an embodiment, a circuit comprises: a first transistor coupledbetween a signal input and a signal output; a second transistor coupledbetween the signal input and a node; a third transistor coupled betweenthe node and the signal output; and a gate control circuit having afirst input adapted to receive an enabling control signal, an outputcoupled to the gates of the first, second and third transistors, and asecond input coupled to the signal input, the gate control circuitoperable in response to a logic transition of the enabling controlsignal to pre-charge a substantially constant gate-to-source voltageacross the first transistor.

In another embodiment, a circuit comprises: a first transistor having asource connected to a signal input, a drain connected to a signaloutput, and a gate; and a gate control circuit having an outputconnected to the gate of the first transistor, and having a first inputconnected to the source of the first transistor, the gate controlcircuit operable in response to a logic transition of an enablingcontrol signal at a second input to pre-charge a substantially constantgate-to-source voltage across the first transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the method and apparatus of the presentinvention may be acquired by reference to the following DetailedDescription when taken in conjunction with the accompanying Drawingswherein:

FIG. 1 is a schematic diagram of a prior art MOS analog switch;

FIG. 2 is a schematic diagram of a prior art MOS analog switch;

FIG. 3 is a schematic diagram of an analog switch embodiment;

FIG. 4 is a schematic diagram of a gate control circuit for use with theanalog switch embodiment of FIG. 3; and

FIG. 5 is a schematic diagram of a gate control circuit for use with theanalog switch embodiment of FIG. 3.

DETAILED DESCRIPTION OF THE DRAWINGS

Reference is now made to FIG. 3 which shows a schematic diagram of ananalog switch 100 embodiment. First NMOS transistor 102 has its sourcecoupled to the input terminal IN, and its drain coupled to the outputterminal OUT. Second NMOS transistor 104 has its source coupled to theinput terminal IN and its drain coupled to node 106. Third NMOStransistor 108 has its source coupled to the node 106 and its draincoupled to the output terminal OUT. Node 106 is further coupled to thebulk terminals (substrate wells) of transistors 102, 104 and 108.

A pre-charge (enable) signal received at the terminal PRE-CHARGE isapplied to a first input of a gate control circuit 110. The gate controlcircuit 110 has an output 132 coupled to the gates of transistors 102,104 and 108 and a second input 134 coupled to the input terminal INPUT.The pre-charge (enable) signal controls whether the analog switch 100 isenabled or disabled for operation to pass a signal from the inputterminal IN to the output terminal OUT. If the pre-charge (enable)signal is in a state (for example, logic low) indicative of a disablecondition, the gate control circuit 110 will turn off the transistors102, 104 and 108. Conversely, if the pre-charge (enable) signal is in astate (for example, logic high) indicative of an enable condition, thegate control circuit 110 establishes a substantially constant voltagedifference between the gate (at output 132) and source (at second input134 and input terminal IN) of the transistor 102. This substantiallyconstant voltage difference between the gate and source of thetransistor 102 is provided regardless of the voltage difference betweenthe source (at second input 134 and input terminal IN) and drain (atoutput terminal OUT) of the transistor 102.

Reference is now made to FIG. 4 which shows a schematic diagram of thegate control circuit 110 for use with the analog switch of FIG. 3. Afourth NMOS transistor 112 is coupled in series with a fifth NMOStransistor 114 between a reference voltage node Vcc and a ground node.Specifically, the drain of fourth transistor 112 is coupled to thereference voltage node Vcc and the source of fourth transistor 112 iscoupled to the gate control node (GATES). The drain of fifth transistor114 is coupled to the gate control node (GATES) and the source of fifthtransistor 114 is coupled to the ground node. The gate of fourthtransistor 112 is coupled to the output of an AND logic gate 116. Afirst input of the exclusive-OR logic gate 116 is coupled directly tothe terminal PRE-CHARGE, while a second input of the exclusive-OR logicgate 116 is coupled indirectly to the terminal PRE-CHARGE through adelay circuit 118 and an inverter 120. The gate of fifth transistor 114is coupled indirectly to the terminal PRE-CHARGE through the inverter120. A capacitor 122 is coupled between the gate control node (GATES) atthe output 132 and the input terminal IN at the second input 134. Thus,the capacitor 122 is connected across the gate-to-source of thetransistors 102 and 104. The capacitor 122 is provided in addition toany parasitic gate-to-source capacitance of the transistor 102 (ortransistor 104). As an example, the capacitor 122 may have a capacitancein the range of a few picofarads for typical audio applications.

When the signal at terminal PRE-CHARGE is in a state (for example, alogic low steady state condition) indicative of a disable condition, theswitch 100 of FIG. 3 is disabled. The gate of fourth transistor 112 isdriven low by AND logic gate 116, and the gate of fifth transistor 114is driven high by inverter 120. Thus, transistor 112 is off andtransistor 114 is on, and the output 132 is grounded. This drives thegate control node (GATES) low, discharges the capacitor 122, and turnsoff transistors 102, 104 and 108 in the switch 100.

When the signal at terminal PRE-CHARGE is in a state (for example, alogic high steady state condition) indicative of an enable condition,the switch 100 of FIG. 3 is enabled. The gate of fifth transistor 114 isdriven low by inverter 120. This turns off transistor 114. Additionally,after a delay period discussed in detail below, the gate of fourthtransistor 112 is driven low by AND logic gate 116. This turns offtransistor 112. In this condition, the capacitor couples the source ofthe transistor 102 (at second input 134) to the gate of the transistor102 (at output 132). In this configuration, the signal received at inputterminal IN is used to drive the gate of transistors 102, 104 and 108(the voltage of the input signal being offset by any voltage across thecapacitor 122 which defines the gate-to-source voltage of transistor102). Since the voltage across the capacitor 122 (defining thegate-to-source voltage of transistor 102) is substantially constant, theon-resistance of the transistor 102 will likewise be substantiallyconstant. In view of this substantially constant gate-to-source voltagefor transistor 102, there exists a low flatness operating characteristicfor the switch 100.

In this context, the voltage across the capacitor 122 is considered tobe “substantially constant” if that voltage varies little, if at all,over a period time in which input signals at terminal IN are beingpassed to the output terminal OUT (while the signal at terminalPRE-CHARGE is in a state indicative of an enable condition). A“substantially constant” voltage may also be evidenced by the existenceof a substantially flat (constant) on-resistance for the transistor 102(between IN and OUT) over widely varying voltages of the input signal(for example, between ground and Vdd).

We now discuss what happens when the signal at terminal PRE-CHARGEtransitions from a state (for example, logic low) indicative of adisable condition to a state (for example, logic high) indicative of anenable condition. The AND logic gate 116 and delay circuit 118 respondto the transition from logic low to logic high at terminal PRE-CHARGE bygenerating a short logic high pulse at the gate of transistor 112. Thispulse will turn on transistor 112 for a short period of time defined bythe length of the delay introduced by delay circuit 118. It will beremembered that transistor 114 is turned off by the logic high signal atthe terminal PRE-CHARGE. While transistor 112 is turned on, the voltagefor the gate control node (GATES) at the output 132 is charged to apre-charge voltage of Vcc−Vthn (where Vthn is the threshold voltage oftransistor 112). This pre-charge voltage produces a voltage acrosscapacitor 122 which defines the substantially constant gate-to-sourcevoltage difference for the transistor 102. For example, the voltagestored across capacitor 122, for Vcc=3.3V, would be 3.3V−0.7V=2.6V.

Since the transistor 102 of FIG. 3 has a substantially constantgate-to-source voltage, regardless of voltage change at the inputterminal IN, the switch 100 exhibits a low flatness operatingcharacteristic. Importantly, the gate control circuit 110 does not havea static discharge path, and thus this implementation is well suited foruse in battery powered applications. Furthermore, the gate controlcircuit 110 tracks the input voltage at the input terminal IN throughthe capacitor 122 and thus is responsive to negative voltages at theinput terminal IN.

The circuit of FIG. 4 is illustrative only, it being understood by thoseskilled in the art how to configure circuits with equivalent operation.The operational point of the gate control circuit 110 of FIG. 3 is toselectively charge a substantially constant gate-to-source voltage withrespect to transistor 102. This is accomplished by charging a voltageacross the capacitor 122 which is connected from gate-to-source oftransistor 102. FIG. 5 illustrates this using a selective charge circuit150 which functions responsive to the signal at the terminal PRE-CHARGEin: a first mode to discharge the voltage on capacitor 122 to ground; asecond mode to charge a substantially constant voltage derived from Vccon the capacitor 122; and a third mode to disconnect Vcc and ground fromthe output 132 (GATES).

CONCLUSION

In order for an analog switch to achieve low flatness, the transistorgate-to-source voltage must remain substantially constant. The prior artimplementation of FIG. 2 level shifts the input signal to provide aconstant gate drive signal for the NMOS transistor. This circuit,however, possesses a static current discharge path and cannot work withsome negative input signal voltages. The circuit of FIGS. 3 and 4,however, provides an improved gate control circuit. The capacitor 122 isplaced between the gate of the NMOS switch transistor and the inputterminal IN (the source of the NMOS switch). When the analog switch isinitially activated, the capacitor is precharged. Thereafter, withrespect to an input signal applied to the input terminal IN, asubstantially constant voltage difference will remain present betweenthe NMOS switch transistor gate and source, relative to thedrain-to-source voltage, providing a low flatness operatingcharacteristic.

Although preferred embodiments of the method and apparatus of thepresent invention have been illustrated in the accompanying Drawings anddescribed in the foregoing Detailed Description, it will be understoodthat the invention is not limited to the embodiments disclosed, but iscapable of numerous rearrangements, modifications and substitutionswithout departing from the spirit of the invention as set forth anddefined by the following claims.

1. A circuit, comprising: a first transistor coupled between a signalinput and an output; a second transistor coupled between the signalinput and a node; a third transistor coupled between the node and theoutput; and a gate control circuit having an output coupled to the gatesof the first, second and third transistors, and having a control inputcoupled to receive a control signal; and a capacitor coupled across thegate-to-source of the first transistor between the signal input and theoutput of the gate control circuit, the gate control circuit comprisingpre-charge circuitry including a delay circuit coupled to the controlinput and adapted to respond to a change in state of the control signalreceived at the control input to generate a pulse signal having a pulseduration set by said delay circuit, said pre-charge circuitry operablein response to the pulse signal to couple a first reference voltage tothe capacitor for the duration of the pulse signal so as to store avoltage across the capacitor which sets a gate-to-source voltage of thefirst transistor.
 2. The circuit of claim 1 wherein the first, secondand third transistors are of the same conductivity type.
 3. The circuitof claim 1 further comprising a connection from the node to a bulk ofeach of the first, second and third transistors.
 4. The circuit of claim1 wherein the delay circuit is adapted to generate the pulse signal whenthe control signal at the control input changes from a logic stateindicating that the first transistor is to be disabled.
 5. The circuitof claim 4 wherein the pre-charge circuitry is adapted to couple asecond reference voltage to the output of the gate control circuit andthe gates of the first, second and third transistors if the controlsignal at the control input has the logic state indicating that thefirst transistor is to be disabled.
 6. The circuit of claim 1 whereinthe delay circuit comprises: a logic gate driven by the control signalat the control input and a delayed version of the control signal at thecontrol input.
 7. The circuit of claim 1 further comprising: a fourthtransistor having a gate coupled to receive the control pulse, thefourth transistor adapted to be turned on by the control pulse tomomentarily couple the first reference voltage to the capacitor and passa charging current to the capacitor; and a fifth transistor coupled inseries with the fourth transistor and adapted to be turned on inresponse to the control signal at the control input so as to turn offthe first transistor, wherein the first, second, third, fourth and fifthtransistors are of a same conductivity type.
 8. The circuit of claim 1 9wherein the gate control circuitry is further operable, followingtermination of the pulse signal after said duration, to disconnect theoutput of the gate control circuitry from both a high supply voltagenode and a low supply voltage node, said high and low supply voltagenodes configured to supply power to said gate control circuitry.
 9. Acircuit comprising: a first transistor coupled between a signal inputand an output; a second transistor coupled between the signal input anda node; a third transistor coupled between the node and the output; anda gate control circuit having an output coupled to the gates of thefirst, second and third transistors, the gate control circuit comprisinga capacitor coupled across the gate-to-source of the first transistorbetween the signal input and the output of the gate control circuit,wherein a voltage stored across the capacitor sets a gate-to-sourcevoltage of the first transistor; wherein the gate control circuitcomprises a pre-charge circuit adapted to pre-charge the gate-to-sourcevoltage across the capacitor, the pre-charge circuit including a controlinput adapted to receive a control signal; wherein the pre-chargecircuit comprises: a pulse circuit adapted to generate a control pulsein response to the control signal at the control input; and a fourthtransistor having a gate coupled to receive the control pulse, thefourth transistor adapted to be turned on by the control pulse and passa charging current to the capacitor; wherein the pulse circuit comprisesa logic gate driven by the control signal at the control input and adelayed version of the control signal at the control input.
 10. Acircuit, comprising: a first transistor having a source coupled to asignal input, a drain coupled to a signal output, and a gate; and a gatecontrol circuit having an output coupled to the gate of the firsttransistor, and having a control input adapted to receive a controlsignal; and a capacitance coupled between the signal input and theoutput of the gate control circuit, the gate control circuit comprisingpre-charge circuitry including a delay circuit coupled to the controlinput and adapted to respond to a change in state of the control signalreceived at the control input to generate a signal pulse having a pulseduration set by said delay circuit that couples, for a length of thepulse duration, a first reference voltage to the capacitance to store avoltage across the capacitance.
 11. The circuit of claim 10 wherein thecapacitance is provided by a capacitor that is coupled between the gateand source of the first transistor.
 12. The circuit of claim 11 furthercomprising a second transistor coupled between the signal input and anode, and a third transistor coupled between the node and the signaloutput, the second and third transistors having gates which are coupledto the gate of the first transistor.
 13. The circuit of claim 11 whereinthe gate control circuitry is further operable, following termination ofthe pulse signal after said duration, to disconnect the output of thegate control circuitry coupled to the gate of the first transistor fromboth a high supply voltage node supplying the first reference voltageand a low supply voltage node supplying a ground reference voltage, saidhigh and low supply voltage nodes configured to supply power to saidgate control circuitry.
 14. A circuit, comprising: a first transistorcoupled between a signal input and a signal output; a second transistorcoupled between the signal input and a node; a third transistor coupledbetween the node and the signal output; and a gate control circuithaving a control input adapted to receive an enabling control signal,and an output coupled to the gates of the first, second and thirdtransistors; and a capacitor coupled between the gate and the source ofthe first transistor, the gate control circuit operable in response to alogic transition of the enabling control signal from a first logic stateto a second logic state to generate a signal pulse, the gate controlcircuit further comprising a switching circuit operable in response tothe enabling control signal in the first logic state to connect theoutput of the gate control circuit to a low reference voltage node,further operable in response to the signal pulse to connect a highreference voltage node to the capacitor for a length of the signal pulseso as to pre-charge a gate-to-source voltage across the firsttransistor, and further operable in response to termination of thesignal pulse to disconnect the output of the gate control circuit fromboth the low reference voltage node and the high reference voltage node.15. The circuit of claim 14 wherein when the output of the gate controlcircuit is connected to the low reference voltage node, the gates of thefirst, second and third transistors are coupled to a reference voltagewhich turns off the first, second and third transistors.
 16. A circuit,comprising: a first transistor having a source connected to a signalinput, a drain connected to a signal output, and a gate; and a gatecontrol circuit having an output connected to the gate of the firsttransistor, and having a control input adapted to receive an enablingcontrol signal; and a capacitance coupled between the signal input andthe output of the gate control circuit, the gate control circuitcomprising a logic circuit with a delay operable in response to a logictransition of the received enabling control signal to couple a highreference voltage node to the capacitance for a length of the delay soas to pre-charge a gate-to-source voltage across the first transistor,the gate control circuit further operable in response to termination ofthe delay to disconnect the output of the gate control circuit connectedto the gate of the first transistor from both the high reference voltagenode and a low reference voltage node, said high and low referencevoltage nodes configured to supply power to said gate control circuit.17. The circuit of claim 16 wherein the capacitance comprises acapacitor connected between the gate and the source of the firsttransistor to store the gate-to-source voltage.
 18. The circuit of claim16 further comprising a second transistor having a source connected tothe signal input, a drain connected to a node and a gate, and a thirdtransistor having a source connected to the node and a drain connectedto the signal output and a gate, the gates of the second and thirdtransistors being connected to the gate of the first transistor.
 19. Thecircuit of claim 16 wherein the gate control circuit comprises apre-charge transistor operable in response to a pulse signal having alength of the delay to couple the high reference voltage node to thecapacitance.